1. Field of the Disclosure
The present disclosure relates to an input circuit, and more particularly to an input circuit configured for use in a high speed counter module, one of extension modules of Programmable Logic Controller (PLC).
2. Discussion of the Related Art
The information disclosed in this Discussion of the Related Art section is only for enhancement of understanding of the general background of the present disclosure and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Generally, a high speed counter module of Programmable Logic Controller (PLC) functions to count a fast pulse signal of a pulse generator or an encoder, and is defined by an extension module for PLC necessary for performing an operation where revolution of a motor is learned at an industrial site.
The high speed counter module uses a high speed pulse to enhance accuracy of pulse counting function, and a conventional high speed counter module uses a Micro Processor Unit (MPU) to count various input signals via interrupt.
However, the MPU using interrupt suffers from a disadvantage in counting high speed pulses that many conditions are required.
FIG. 1 is a schematic view illustrating a pulse input method of a high speed counter module of PLC according to prior art, and FIGS. 2A, 2B, and 2C are schematic views illustrating a counting method of a pulse input module of FIG. 1, where FIG. 2A illustrates 1-phase/2-input/1-multiplication mode, FIG. 2B illustrates 2-phase/4-multiplication mode, and FIG. 2C illustrates clockwise (CW)/counterclockwise (CCW) counting mode.
Referring to FIG. 1, FIG. 2A, FIG. 2B, and FIG. 2C, an encoder (100) generally outputs a 1-phase pulse or a 2-phase pulse, and an MPU (200) of PLC receives a rising edge or a falling edge of the pulse via an interrupt to count the pulses. The MPU (200) generally counts pulses via 1-phase/2-input/1-multiplication mode, 1-phase/2-input/2-multiplication mode, 2-phase/1-multiplication mode, 2-phase/2-multiplication mode, 2-phase/4-multiplication mode, or CW/CCW mode, where a type of counting and states of adding/deducting are checked to perform the addition/deduction operations. In the conventional counting method, the rising edge/falling edge are detected and all the counting operations must be completed before detection of next edges.
A phase in FIG. 2A (1-phase/2-input/1-multiplication mode) is a pulse to be counted, and B phase is addition/deduction state. FIG. 2B (2-phase/4-multiplication mode) shows a state in which the A phase is compared with the B phase, and if phase of the A phase is ahead, addition is made and if phase of the A phase is behind, deduction is made. FIG. 2C (CW/CCW) shows a state in which input of the A phase is added, while input of the B phase is deducted.
As noted from the foregoing, the MPU (200) detects rising edge/falling edge of interrupt connected to the pulse input to process a service routine of the interrupt. FIG. 3A and FIG. 3B are flowcharts illustrating interrupt process routine of a conventional MPU in 2-phase/4-multiplication mode, where FIG. 3A illustrates an A phase interrupt routine, and FIG. 3B illustrates a B phase interrupt routine.
In a case A phase and B phase interrupt process routines are started (S301, S311), a multiplication mode is first checked (S302, S312). The multiplication mode includes, as explained above, 1-phase/2-input/1-multiplication mode, 1-phase/2-input/2-multiplication mode, 2-phase/1-multiplication mode, 2-phase/2-multiplication mode, 2-phase/4-multiplication mode and CW/CCW mode, where methods of classifying addition and deduction for each mode are different, and other modes are performed in case of the multiplication mode not being the 2-phase/4-multiplication mode (S304, 314).
In case of the multiplication mode being 2-phase/4-multiplication mode (S303, S313), the A phase interrupt routine (FIG. 3A) performs addition in case of A phase and B phase being different, and performs deduction in case of A phase and B phase being identical (S305. S307), and alternatively B phase interrupt routine performs the addition/deduction (S315 to S317). In the same manner, addition/deduction is classified in 2-phase/1-multiplication mode and 2-phase/2-multiplication mode. After addition/deduction, over/under flows are checked (S308, 5318) and additional function is finally performed (A309, S319).
FIG. 4 is a flowchart illustrating an interrupt process routine of a conventional MPU in 1-phase/2-input/1-multiplication mode.
In a case the interrupt process routine is started (S401), a multiplication mode is first checked (S402). In case of 1-phase/2-input/1-multiplication mode (S403), addition/deduction is classified through B phase level. 1-phase/2-input/2-multiplication mode is also classified in the same manner. That is, in case of B phase being LOW (S405), addition is performed at a rising edge of A phase (S406, S407), and deduction is performed (S408, 5409) at a falling edge of A phase in case of B phase being HIGH (S405). The addition/deduction is not performed when B phase is HIGH at a rising edge of A phase, and when B phase is LOW at a falling edge of A phase.
As noted from the foregoing, the high speed counter module for PLC according to prior art is such that an operation mode is first classified during pulse input, and counting operation is performed after grasp of addition/deduction states. There are various input modes, and differently processes in response to operation edges of each mode. The process routine must be completely finished, at least before a next pulse is inputted. The MPU (200) must perform other functions than the high speed counting, such that the interrupt routine counting pulses needs to be shortened to the maximum.
FIG. 5 is a schematic view illustrating a problem encountered during interrupt process routine of MPU at 2-phase/4-multiplication mode, where a problem occurs in which as the frequency of input pulse increases, a next pulse is inputted before the interrupt routine is processed. As noted above, in a case an interrupt period is equal to or shorter than an interrupt routine process time, the MPU (200) disadvantageously performs a high speed count only, or performs an erroneous operation by omitting an input pulse.